Current electronic equipment uses semiconductor devices, such as, for example, memory devices and data processing devices. For example, mobile electronic devices such as digital cameras, portable digital assistants, portable audio/video players and mobile terminals continue to require mass storage memories, such as non-volatile memory, with ever increasing capacities and speed capabilities. Non-volatile memory and hard-disk drives are often used since data is retained in the absence of power, thus extending battery life.
While existing memory devices operate at speeds sufficient for current electronic equipment, such memory devices may not be adequate for use in future electronic products and other products where high data rates are desired. For example, a mobile multimedia device that records high definition moving pictures is likely to require a memory module with a greater programming throughput than is available with current memory technology. While such a solution appears to be straightforward, there is a problem with signal quality at such high frequencies that sets a practical limitation on the operating frequency of the memory. The memory communicates with other components using a set of parallel input/output (I/O) pins, the number of which depends on the desired configuration. The I/O pins receive command instructions and input data and provide output data. This is commonly known as a parallel interface. High speed operation may cause communication degrading effects such as cross-talk, signal skew and signal attenuation, for example, which degrades signal quality.
In order to incorporate higher density and faster operation on the system boards, there are two design techniques possible: multi-drop and serial interconnection configurations. These design techniques may be used to overcome the density issue that determines the cost and operating efficiency of memory swapping between a hard disk and a memory system. However, multi-drop configurations have shortcomings relative to the serial interconnection of memory systems. For example, if the number of multi-drop memory systems increases, as a result of the loading effect of each pin, the delay time also increases so that the total performance of multi-drop is degraded by the multi-drop connection caused by the wire resistor-capacitor loading and the pin capacitance of the memory device. A serial link may provide a serial interconnection configuration to control command bits, address bits, and data bits effectively through the serial interconnection. In the serial interconnection configuration, each device is identified by a device identifier or a device address. Memory devices may be dynamic random access memories (DRAMs), static random access memories (SRAMs) and any type of flash memories.
For serial links operating at slow speeds in system applications, existing circuits for capturing data streams can be employed and result in acceptable performance. However, in the case of high speed operation, the correct data capturing from a serial port to assigned registers is not ensured in existing circuits because of fast clock operation during command interpretation.